Senior Engineer - RegE Process Development (3D NAND)

About the role

Micron Technology, a global leader in memory and storage solutions, is hiring a Senior Engineer for its regE process development team at Fab10N/X. The role owns regE process characterisation and advanced process development for 3D NAND and beyond, working with process development engineers in Singapore and vendors to deliver processes that meet integration requirements for next-generation 3D NAND nodes.

Key responsibilities

• Own regE process characterisation and advanced process development for 3D NAND and beyond
• Develop regE processes with Singapore-based engineers and vendors that meet integration requirements for next-generation 3D NAND nodes
• Transfer regE processes to high-volume manufacturing (Fab10) and drive continuous improvements to manufacturability
• Address wafer edge issues such as bevel defects and uniformity, working with the Fab10N team and business partners on tool choices
• Improve regE process margins to meet the mature yield goal for 3D NAND parts, and run experiments to widen margins and test next-node manufacturability
• Incorporate best-known manufacturing methods into early development of upcoming nodes
• Design and implement advanced process monitoring and control methodologies
• Serve as a technical expert on process, procedure and equipment improvement projects, and lead complex, multi-functional projects and teams on quality, yield, cost and productivity improvement
• Advise management on major technical issues, lead innovation projects through patents and technical papers, and collaborate with suppliers worldwide
• Use Micron-approved AI tools responsibly for productivity and quality, keeping confidential information secure

Required profile

• Ph.D. in Materials Science, Chemical Engineering or Physics, or a Bachelor's/Master's degree in the same fields with at least 3 years of hands-on experience in regE process development
• Familiarity with regE process development and yield improvement
• Understanding of integration and structural constraints related to wafer edge, and of planar and vertical NAND process flows
• Self-motivated, adaptable to extended hours, and able to prioritise multiple projects in a demanding environment

Required skills

• Working knowledge of data analysis systems such as Y3
• Working knowledge of Design of Experiments (DoE)