Foundation IP Design Engineer

About the role

We are seeking an energetic and passionate memory design engineer to join our Central Engineering Group. You will become part of an elite memory team that develops cutting‑edge memory compilers and custom macros across the latest process technologies.

Key responsibilities

• Analyze various memory architectures and assess trade‑offs.
• Design and implement memory or circuit blocks at the gate or transistor level.
• Run transistor‑level simulations, perform post‑layout verification, and extract layouts.
• Floorplan physical implementations and integrate leaf‑cell layouts to build physical macros.
• Develop and integrate characterization flows to extract timing and power data.
• Write automation scripts for characterization, simulation, and verification tasks.
• Specify, verify, and document behavioral and physical memory models.
• Create silicon test plans, correlate silicon results with simulations, and debug silicon issues.

Required profile

• BS in Electrical Engineering.
• 5+ years of experience in memory or digital IP design.
• Strong self‑motivation, ability to multitask, and good communication skills.

Required skills

• Memory compiler development and custom digital circuit design (SRAM, register files, multi‑port memories, ROM).
• Deep understanding of transistor‑level circuit behavior, device physics, signal integrity, EM/IR, and reliability analysis.
• Experience with behavioral and physical memory models, DFT schemes, and chip‑level integration.
• Proficiency in transistor‑level simulators, post‑layout verification tools, and automation scripting.
• Familiarity with silicon test setups and debugging is a plus.

What we offer

• Opportunity to work on bleeding‑edge process technologies.
• Collaborative environment within a high‑performing memory team.