Foundation IP Design Engineer

About the role

We are seeking an energetic and passionate IP Design Engineer to join our Central Engineering Group. You will work on cutting‑edge memory compilers and custom macro development, contributing to the creation of high‑performance memory blocks on advanced process technologies.

Key responsibilities

• Analyze various memory architectures and assess trade‑offs.
• Design and implement memory or circuit blocks at the gate or transistor level.
• Run transistor‑level simulations, extract layouts, and perform post‑layout verification.
• Floorplan physical implementation and integrate leaf‑cell layouts into full macros.
• Develop and automate characterization flows to extract timing and power data.
• Create and verify behavioral and physical memory models.
• Document specifications, behavioral descriptions, and timing diagrams.
• Define silicon test plans, correlate silicon results with simulations, and assist in debugging silicon issues.

Required profile

• BS in Electrical Engineering or related field.
• At least 2 years of experience in memory compiler development or custom digital circuit design.
• Strong understanding of transistor‑level behavior, device physics, and signal integrity.
• Good communication, interpersonal, and leadership abilities.

Required skills

• Memory compiler development (SRAM, register files, multi‑port, ROM).
• Transistor‑level circuit simulation and layout extraction.
• Signal integrity, EM/IR, and reliability analysis.
• Memory behavioral and physical modeling.
• Design‑for‑test (DFT) schemes and chip‑level integration.
• Silicon testing and debug (plus).
• Automation scripting for characterization, simulation, and verification.