Staff Silicon Design Engineer

About the role

As a Staff Silicon Design Engineer you will lead the verification of ASIC and FPGA System‑on‑Chip designs, planning, developing and executing test strategies to ensure bug‑free silicon.

Key responsibilities

• Work as a member of a geographically distributed SoC verification team to verify next‑generation ASIC and FPGA SoCs.
• Collaborate with design, software and architecture teams to verify SoC design under test.
• Develop SoC test plans, implement testbenches, create test cases, and ensure functional coverage closure.
• Handle regression testing and contribute to verification infrastructure development.
• Develop both directed and random verification tests.
• Debug test failures, identify root causes, and work with RTL and firmware engineers to resolve design defects.
• Review functional and code coverage metrics, modify or add tests or constrain random tests to meet coverage requirements.

Required profile

• Passion for next‑generation FPGA and ASIC design verification.
• Team player with excellent communication skills and experience collaborating across sites and time zones.
• Strong analytical and problem‑solving abilities.
• Eager to learn and take on challenging tasks.
• Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering with relevant experience.

Required skills

• SoC and IP‑level FPGA/ASIC verification.
• Proficiency in Verilog and SystemVerilog.
• Experience with C and C++.
• Scripting in Perl or Python.
• Hands‑on experience with SystemVerilog and UVM (mandatory).
• Development of UVM‑based verification testbenches, processes and flows.
• Understanding of SoC architecture, design flow and verification methodology.