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Principal Engineer - Hardware Sustaining

hpe · Singapore

New
Senior 🇬🇧 English
Verilog RTL FPGA CPLD SerDes DDR PCIe Signal Integrity Power Integrity PLM Schematic Capture Layout

Job description

About the role

Hewlett Packard Enterprise's Hardware Sustaining organization within the Networking Products and Technologies (NPAT) group drives product hardware quality to ensure a best-in-class customer experience. This Principal Engineer role leads hardware failure analysis on HPE networking products and is designed as onsite, with the expectation of working primarily from an HPE office.

Key responsibilities

  • Lead failure analysis of complex hardware problems, covering CPU, networking ASICs, power, clocking, high-speed signals, optics and more.
  • Drive corrective and preventive actions: immediate containment or work-arounds, validation of the final fix, identification of other affected systems, and sharing lessons learned to prevent recurrence.
  • Provide technical leadership in hardware quality and reliability, guide and mentor junior team members, and collaborate with engineering, manufacturing, ODM and supply chain teams.
  • Document findings and lessons learned, and give regular failure analysis updates and final RCCA reports to internal stakeholders and customer support teams.

Required profile

  • Bachelor's or Master's degree in electrical engineering (12+ years of experience, or 10+ years with a Master's).
  • Proven track record of driving root cause and corrective action on complex hardware, preferably in the networking domain.
  • Leadership and subject-matter expertise, with the ability to mentor others and collaborate across functions.
  • Demonstrated experience in a technical leader or subject-matter expert role.

Required skills

  • Expertise in hardware design processes and tools such as schematic capture, layout, BoM and PLM tools.
  • Debugging of networking hardware, including 20-layer boards with 50G+ signals, and signal and power integrity.
  • Design and debug of high-speed (PCIe, SerDes, DDR) and low-speed (I2C, SPI) interfaces, plus FPGA and CPLD design and debug with Verilog RTL.
  • Proficiency in scripting for hardware design, test and debug.
  • Excellent written and verbal communication in English and the local language.

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Source : ats:workday

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Published 7 hours ago

Expires 1 month from now

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hpe

Singapore