Research Associate – RISC‑V Hardware AES & ASCON Accelerator

About the role

We are seeking a Research Associate to integrate hardware cryptographic accelerators into the RISC‑V CVA6 core at the School of Electrical and Electronic Engineering, NTU Singapore. The role focuses on adding AES and ASCON accelerators and extending the ISA to support them.

Key responsibilities

• Design and integrate a hardware AES accelerator and an ASCON lightweight cryptography accelerator into the RISC‑V CVA6 (Ariane) core.
• Develop memory‑mapped interfaces or custom instructions for accelerator communication with the core.
• Modify the CVA6 decode and execution stages to handle new cryptographic instructions.
• Extend the toolchain (assembler, compiler, simulation) to support custom instructions.
• Conduct simulations and performance testing to evaluate latency, throughput, and integration quality.
• Collaborate closely with accelerator designers to debug and verify hardware integration.

Required profile

• Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
• Proven experience with RISC‑V architecture, especially custom instruction extensions and pipeline modifications.
• Strong background in hardware design and cryptographic algorithm implementation.

Required skills

• HDL proficiency (Verilog, VHDL, or SystemVerilog) and RTL design.
• Toolchain modification experience (GCC, LLVM) for custom instructions.
• FPGA development tools such as Vivado or Quartus.
• Understanding of ASIC/FPGA design flows, synthesis, place‑and‑route, and timing closure.
• Knowledge of AES and ASCON cryptographic algorithms.