Senior IC Design Engineer – Design Verification

About the role

We are looking for a Senior IC Design Engineer specialized in design verification to join our island‑wide team in Singapore. You will lead verification activities for pre‑silicon IP, ASIC and SoC projects, ensuring functional correctness and high coverage.

Key responsibilities

• Develop and execute verification plans based on design specifications.
• Build and maintain SystemVerilog/UVM verification environments and testbenches.
• Create directed and constrained‑random tests, assertions (SVA), and functional coverage models.
• Debug DUT issues, analyze simulation results, and drive verification closure.
• Collaborate with cross‑functional teams throughout the design and verification lifecycle.
• Support regression automation and continuously improve verification methodologies.
• Leverage AI‑assisted tools and data‑driven techniques to boost verification efficiency and debug productivity.

Required profile

• Bachelor's or Master's degree in Electrical, Electronic, Computer Engineering or a related field.
• At least 1 year of hands‑on experience in ASIC/SoC/IP verification.
• Strong analytical, problem‑solving and communication skills.

Required skills

• SystemVerilog and UVM.
• Constrained‑random verification, assertions (SVA) and functional coverage.
• Scripting languages such as Python, Perl or Tcl.
• Experience with industry‑standard EDA tools (e.g., Cadence or Synopsys).
• Familiarity with AI/ML‑assisted EDA tools is a plus.