Senior PHY Design Engineer

About the role

We are looking for a Senior PHY Design Engineer to lead the development of high‑speed DDR PHY IP in our Singapore R&D centre. The role involves end‑to‑end analog circuit design, signal integrity analysis, and silicon validation for next‑generation memory interfaces.

Key responsibilities

• Design high‑speed analog circuits for DDR4/DDR5/LPDDR5/6 PHYs, including PLLs, DLLs, TX/RX channels, ODT, CTLE/DFE, and voltage regulators, while optimizing power, performance, area and signal integrity.
• Perform SI/PI analysis, model channel losses, crosstalk, jitter and generate eye diagrams to meet JEDEC DDR5‑6400 MT/s specifications.
• Adapt designs to advanced FinFET nodes (7 nm/5 nm and below), handling PVT variations and reliability concerns such as TDDB and EM/IR.
• Develop test plans, run lab characterisation and ATE, debug silicon failures using oscilloscopes, BERTs and protocol analyzers, and conduct shmoo and margin analysis.
• Collaborate with digital, verification, firmware, package and PCB teams to ensure successful PHY integration and SI/PI optimisation.

Required profile

• Bachelor’s degree or higher in Electrical/Electronic Engineering.
• Minimum 8 years of relevant semiconductor experience.
• Hands‑on experience with DDR protocols (JEDEC DDR4/5, LPDDR5/6) and high‑speed I/O (>6.4 Gbps).
• Proven track record of tape‑out in FinFET/SOI technologies.
• Familiarity with SerDes, HBM or similar high‑speed interfaces is a plus.

Required skills

• Cadence Virtuoso, Spectre, HSPICE, ADS, EMX.
• DDR4, DDR5, LPDDR5, LPDDR6 protocol knowledge.
• Analog design fundamentals: noise analysis, stability, feedback.
• Python, MATLAB, Verilog‑A/AMS scripting.
• FinFET/SOI process design, SI/PI modelling tools.