Digital Design and Implementation Engineer

About the role

GlobalFoundries is looking for a Digital Design and Implementation Engineer interested in semiconductor and digital test-chip design. The role involves designing and implementing Design-of-experiment (DoE) blocks for standard cells and memory test-chips using a digital flow, supporting technology yield development and IP characterization. It offers hands-on experience across the digital design flow, including RTL development, synthesis, floorplanning, place and route, physical verification and timing analysis.

Key responsibilities

• Develop DoE blocks for standard cells and memory macros to support yield measurements and characterization.
• Create and modify RTL, iterating parameters for optimal cell utilization within timing constraints.
• Drive the full digital implementation flow: synthesis, floorplan, power mesh and place and route.
• Run physical verification (DRC, LVS, DFM, MAS) and resolve violations.
• Perform timing extraction and static timing analysis to close timing.
• Execute logical equivalence checks to ensure design integrity.

Required profile

• Degree in Electrical / Electronic Engineering or a related field.
• Experience in digital physical design is preferred.

Required skills

• Preferred: basic Verilog, Python or Ticker coding or equivalent.
• Preferred: basic knowledge of Synopsys digital tools (VCS, ICC2) or Cadence digital tools (Genus, Innovus, Virtuoso).